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I nterlocked Operations Having atomic reads and writes of single memory words is useful, but there is a limit to what can be done with this capability It's generally not feasible to implement a critical region primitive based on it, for instance, because doing so requires multiple memory operations For situations like this, processors offer special primitive instructions specifically for atomic loads and stores in addition to more sophisticated compare-and-swap style operations (aka CAS), wherein a memory location may be modified atomically based on some condition Other kinds of low-level primitives can be built on top of these special interlocked instructions, such as critical regions, events, and lock free code Interlocked operations also imply certain kinds of memo ry fences that inter act with the memory model of the system very directly-and in fact there are variants of them that allow you to control which kinds are used-but we will wait to discuss this until the dedicated section on fences coming shortly Interlocked instructions use interprocessor synchronization in the hard ware Years ago, in the pre-Pentium Pro architectures, issuing an interlocked instruction asserted a lock on the entire system bus while it ran These days, interlocked operations execute within the purview of the cache coherence hardware, using a special mutual exclusive mode when acquiring cache lines This dramatically reduces their cost These instructions are still not

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cheap, however, and still do sometimes lock the bus when contention is high or when accessing a misaligned address A common misconception is that interlocked operations will not work at all on misaligned addresses While this can be less efficient (due to the bus lock noted above) and leads to faults on IA64 as with ordinary load and store instructions, atomicity will never be compromised In any case, an interlocked operation typically costs in the neighborhood of hundreds of cycles: typically 50 to 1 50 cycles on single-socket architec tures, but reaching costs as high as 500 cycles on multisocket architectures NUMA machines will incur even larger overheads, due to internode syn chronization Generally speaking, the more complicated and greater in size the memory hierarchy on the target architecture, the more costly synchro nization operations will be, and the more impact to system scalability they will present It is therefore critical when building low-level software to reduce the number of interlocked operations issued to a minimum

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We now consider another very useful and frequently occurring discrete probability distribution The binomial distribution assumes that the probability of an event remains constant from trial to trial This is not always an accurate assumption We actually have encountered this situation when we studied acceptance sampling in the previous chapter; now we make the situation formal As an example, suppose that a small manufacturer has produced 11 machine parts in a day Unknown to him, the lot contains three parts that are not acceptable (D), while the remaining parts are acceptable and can be sold (G) A sample of three parts is taken, and the sampling being done without replacement; that is, a selected part is not replaced so that it cannot be sampled again This means that after the rst part is selected, no matter whether it is good or defective, the probability that the second part is good depends on the quality of the rst part So the binomial model does not apply We can, for example, nd the probability that the sample of three contains two good and one unacceptable part This event could occur in three ways P(2G, 1D) = P(GGD) + P(GDG) + P(DGG) = 8 11

The most basic interlocked primitive is exchange: it enables you to read a value and exchange it with a new one as a single, atomic action On X86based instruction sets, this translates into an instruction called XCHG Unless you're programming in assembly, or looking at disassembled code, you won't see this instruction being used directly-there are higher level APls that we'll look at momentarily Most other instructions that we'll look at also require a LOCK prefix to be emitted in the assembly code for them to be truly atomic across multiple processors, but XCHG is the one instruction that differs in this regard: a LOC K prefix is implied by its usage Since most of us aren't programming in assembly, there are Win32 and NET APls available from W i n dows h that allow you to utilize the XCHG primitive

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