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II Wait for t h re a d s to f i n i s h c hoo s i n g while ( c hoos i ng [ j ] ! = a ) 1 * b u s y wa it * 1 I I Wait for t h o s e with lower t i c ke t s to f i n i s h If w e took I I the same t i c ket number a s another t h read , t h e one with the I I lowe st ID get s to go first i n stead int j n j wh i l e j n numbe r [ j ] ) ! = a && ( j n < n umber [ i ] I I ( j n == numbe r [ i ] && j < i ) 1 * bus y wait * 1 j

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} II O u r t i c ket wa s c a lled Proceed to o u r region } void LeaveCrit i c a l Region ( i nt i )

* This chapter is derived with permission from 5 of Bragg, Cost Accounting (Hoboken, NJ: John Wiley & Sons, 2001)

This algorithm is also unique when compared to previous efforts because threads are truly granted fair entrance into the region Tickets are assigned on a first-come, first-served basis (FIFO), and this corresponds directly to the order in which threads enter the region

6

Hardware Compare and Swap Instructions (Fast Forward to Present Day) Mutual exclusion has been the subject of quite a bit of research It's easy to

.

Data Tracking Costs by Cost Type Proportion of Total Tracking Costs 15% 65% 20% 100%

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take i t all for granted given how ubiquitous and fundamental synchro nization has become, but nevertheless you may be interested in some of the references to learn more than what's possible to describe in just a few pages (see Further Reading, Raynal) Most of the techniques shown also share one thing in common Aside from the bakery algorithm, each relies on the fact that reads and writes from and to natural word-sized locations in memory are atomic on all modern processors But they specifically do not require atomic sequences of instruc tions in the hardware These are truly "lock free" in the most literal sense of the phrase However, most modern critical regions are not implemented using any of these techniques Instead, they use intrinsic support supplied by the hardware One additional drawback of many of these software only algorithms is that one must know N in advance and that the space and time complexity of each algorithm depends on N This can pose serious challenges in a sys tem where any number of threads-a number that may only be known at runtime and may change over time-may try to enter the critical region Windows and the CLR assign unique identifiers to all threads, but unfor tunately these identifiers span the entire range of a 4-byte integer Making N equal to 2/\32 would be rather absurd Modern hardware supports atomic compare and swap (CAS) instruc tions These are supported in Win32 and the NET Framework where they are called interlocked operations (There are many related atomic instruc tions supported by the hardware This includes an atomic bit-test-and-set instruction, for example, which can also be used to build critical regions We'll explore these in more detail in 1 0, Memory Models and Lock Freedom) Using a CAS instruction, software can load, compare, and con ditionally store a value, all in one atomic, uninterruptible operation This is supported in the hardware via a combination of CPU and memory sub system support, differing in performance and complexity across different architectures Imagine we have a CAS API that takes three arguments: (1 ) a pointer to the address we are going to read and write, (2) the value we wish to place into this location, and (3) the value that must be in the location in.

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The J4L Barcodes are integrated in Eclipse Birt 4.3 or later. The components support 1D barcodes, PDF417, Datamatrix , QRCode, Azteccode and Maxicode.

This can be simpli ed to A = 4 1 + p + p2 + p3 13p4 + 15p5 5p6 A graph of A as a function of p is shown in Figure 62

makes no additional restrictions for such variables, requiring a program mer to thoroughly annotate variables as v o l a t i l e where introduction or removal would be a problem, but NET does As an example of when a load might be introduced, consider this code

MyObj e c t mo = ; int f mo field ; if ( f e)

Proportion of Total Costs 40% 10% 50% 100%

= ==

575 55 525 5 475 45 425 02 04 p 06 08 1

{ II }

Console Writ e L i n e ( f ) ;